1. Field of the Invention
The present invention relates to a direct memory access transfer apparatus in which a data transfer between memories are directly performed through no central processing unit to process a large amount of picture data (or pixel data) relating to motion search or picture characteristic calculation performed in a picture processing system.
2. Description of Related Art
FIG. 10 is a block diagram showing the configuration of a picture processing system having a conventional direct memory access transfer apparatus. In FIG. 10, 100 indicates a memory of a data sender. 101 indicates a memory of a data receiver. 102 indicates a central processing unit (CPU). 103 indicates a conventional direct memory access (DMA) transfer apparatus. 104 indicates an address bus. 105 indicates a data bus.
Next, an operation of a picture processing system is described.
The case where picture data stored in the sender""s memory 100 is sent to the receiver""s memory 101 is, for example, described. A start address of the sender""s memory 100, a start address of the receiver""s memory 101 and the amount of data to be transferred is sent from the CPU 102 to the conventional DMA transfer apparatus 103, and an operation of the conventional DMA transfer apparatus 103 is started. In this operation of the conventional DMA transfer apparatus 103, a readout address of the sender""s memory 100 is output to an address bus 104, and a readout signal is output from the conventional DMA transfer apparatus 103 to the sender""s memory 100. Thereafter, pixel data corresponding to the readout address in the sender""s memory 100 is output from the sender""s memory 100 to the data bus 105.
The pixel data output to the data bus 105 is temporarily stored in a buffer of the conventional DMA transfer apparatus 103. Thereafter, a write address of the receiver""s memory 101 is output from the conventional DMA transfer apparatus 103 to the address bus 104, and a write signal is output from the conventional DMA transfer apparatus 103 to the receiver""s memory 101. Thereafter, the pixel data stored in the buffer of the conventional DMA transfer apparatus 103 is output to the data bus 105, and the pixel data output to the data bus 105 is stored in an area of the receiver""s memory 101 indicated by the write address. Therefore, a data transfer between the sender""s memory 100 and the receiver""s memory 101 can be performed in the picture processing system according to the above-described processing.
For example, the case where a motion search processing in a picture coding is performed in the picture processing system is considered. In this processing, for a rectangular area of 16*16 pixels, all integral-numbered pixels placed from the xe2x88x9216-th relative pixel position to the +15-th relative pixel position are searched in the lateral and longitudinal directions. In this case, when a picture screen size having 352 (16*22) pixels in the lateral direction and 288 (16*18) pixels in the longitudinal direction is set at a frame rate of 30 Hz, the number of additions of differential absolute values between pixels required for every second is expressed according to a following equation.
(frame rate)*(the number of rectangular areas in one screen)*(the number of pixels in one rectangular area)*(the number of search operations)=30*(22*18)*16*16*(15+16+1)2≈3*109
To reduce a large number of addition operations expressed by the above equation, a following approximation calculation is generally known. In this approximation calculation, the pixels of each rectangular area are, for example, sub-sampled at the sample ratio of 2:1 according to a quincunx method to halve the number of additions of differential absolute values.
FIG. 11 is a conceptual view showing a sub-sampling performed at the sample ratio of 2:1 according to the quincunx method. As shown in FIG. 11, a group of pieces of pixel data of pixels arranged at even-numbered positions of one lateral line and a group of pieces of pixel data of pixels arranged at odd-numbered positions of another lateral line are alternately sampled for every lateral line.
This approximation calculation is not limited to the motion search. That is, in cases where a dispersed value of pixels of each rectangular area is calculated as a parameter indicating a characteristic of the rectangular area, an approximation calculation can be performed by sampling pieces of pixel data of the rectangular area at the sample ratio of 2:1 according to the quincunx method.
However, because the conventional DMA transfer apparatus has the above configuration, the conventional DMA transfer apparatus has no circuit mechanism in which pieces of pixel data are sub-sampled to reduce the number of calculations. Therefore, in cases where pieces of pixel data are, for example, sub-sampled at the sample ratio of 2:1 shown in FIG. 11, it is required to perform the sub-sampling of the pixel data according to a software processing performed in the CPU 102. In this case, there is a problem that it takes a lot of time to perform the sub-sampling of the pixel data according to the software processing.
Also, in cases where the data transfer operation is performed for every pixel (for example, for every 8 bits) and an address producing method is adapted to the data transfer operation, a data sub-sampling and the transfer of sub-sampled data can be performed in the conventional DMA transfer apparatus. However, it is required to read pixel data from the sender""s memory 100 for every pixel. Therefore, there is another problem that it takes a lot of time to transfer a large amount of pixel data.
An object of the present invention is to provide, with due consideration to the drawbacks of the conventional DMA transfer apparatus, a direct memory access transfer apparatus in which pieces of pixel data read out from a memory of a data sender are transferred to a memory of a data receiver at a high speed on condition that the accessing of the pieces of pixel data to each of the memories is possible at one time.
The object is achieved by the provision of a direct memory access transfer apparatus, in which pieces of pixel data are transferred between a sender""s memory, to which the accessing of pieces of pixel data is possible at one time, a receiver""s memory to which the accessing of pieces of pixel data is possible at one time, comprising a group of transfer parameter registers for storing a plurality of parameters required to transfer address data of both the sender""s memory and the receiver""s memory, a sender-memory control unit for producing a plurality of two-dimensional readout addresses of the sender""s memory according to the parameters stored in the group of transfer parameter registers and reading out pieces of pixel data corresponding to pixels arranged on a plurality of lateral lines of a rectangular area from the sender""s memory according to the two-dimensional readout addresses of the sender""s memory, a data transforming unit for performing a sub-sampling for the pieces of pixel data of each lateral line read out from the sender""s memory by the sender-memory control unit at a sample ratio of n:1 (n is an integral number higher than 1) and outputting pieces of sub-sampled pixel data corresponding to each lateral line, a receiver-memory control unit for producing a plurality of two-dimensional write addresses of the receiver""s memory according to the parameters stored in the group of transfer parameter registers and write the pieces of sub-sampled pixel data of the lateral lines produced by the data transforming unit in the two-dimensional write addresses of the receiver""s memory, and a timing control unit for controlling a processing timing of the sender-memory control unit, a processing timing of the data transforming unit and a processing timing of the receiver-memory control unit.
In the above configuration, pieces of pixel data are read out from the sender""s memory at one time under the control of the sender-memory control unit, the pieces of pixel data are sub-sampled in the data transforming unit to produce pieces of sub-sampled pixel data, and the pieces of sub-sampled pixel data are written in the receiver""s memory under the control of the receiver-memory control unit.
Accordingly, the pieces of pixel data can be sub-sampled and transferred at a high speed in a DMA transfer apparatus.
Also, because the pieces of pixel data read out from the sender""s memory are sub-sampled in the data transforming unit, the sub-sampling processing for the pieces of pixel data can be performed at a high speed.
It is preferred that the sub-sampling is performed by the data transforming unit according to a quincunx method in which positions of pixels corresponding to the pieces of sub-sampled pixel data of each even-numbered lateral line differ from those corresponding to the pieces of sub-sampled pixel data of each odd-numbered lateral line.
Accordingly, the sub-sampling of pieces of pixel data of pixels placed at fixed longitudinal rows of the rectangular area can be prevented in the direct memory access transfer apparatus.
It is also preferred that sample mode information indicating the performance of a sub-sampling or a full sampling for the pieces of pixel data read out from the sender""s memory is stored in the group of transfer parameter registers, and the sub-sampling or the full sampling is performed for the pieces of pixel data read out from the sender""s memory by the data transforming unit according to the sample mode information stored in the group of transfer parameter registers.
Accordingly, the sub-sampling or the full sampling can be selected.
It is also preferred that the sender-memory control unit comprises an address calculating circuit for calculating each of the readout addresses of the sender""s memory according to the parameters stored in the group of transfer parameter registers, a register for storing the readout addresses calculated in the address calculating circuit, and an output control circuit for outputting the readout addresses stored in the register and a readout signal, which indicates the readout of the pieces of pixel data stored in the sender""s memory, according to an instruction sent from the timing control unit.
Accordingly, the readout addresses of the sender""s memory can be obtained, and the pieces of pixel data corresponding to the readout addresses can be read out from the sender""s memory.
It is also preferred that the receiver-memory control unit comprises an address calculating circuit for calculating each of the write addresses of the receiver""s memory according to the parameters stored in the group of transfer parameter registers, a register for storing the write addresses calculated in the address calculating circuit, and an output control circuit for outputting the write addresses stored in the register and a write signal, which indicates the writing of the pieces of sub-sampled pixel data produced by the data transforming unit, according to an instruction sent from the timing control unit.
Accordingly, the write addresses of the receiver""s memory can be obtained, and the pieces of sub-sampled pixel data can be written in the write addresses of the receiver""s memory.
It is also preferred that the data transforming unit comprises a register for storing the pieces of pixel data read out from the sender""s memory according to an instruction sent from the timing control unit, a sub-sampling circuit for performing the sub-sampling or the full sampling for the pieces of pixel data stored in the register according to the sample mode information stored in the group of transfer parameter registers to produce pieces of sampled pixel data and transforming the pieces of sampled pixel data into a piece of a combined pixel data corresponding to the lateral line according to an instruction sent from the timing control unit, and an output control circuit for outputting the combined pixel data of the lateral line transformed in the sub-sampling circuit according to an instruction sent from the timing control unit.
Accordingly, the sub-sampling or the full sampling for the pieces of pixel data can be performed for every lateral line, and the pieces of sampled pixel data can be output as the combined pixel data for every lateral line.
It is also preferred that the data transforming unit comprises a register for storing the pieces of pixel data read out from the sender""s memory according to an instruction sent from the timing control unit, an odd-even judging circuit for judging according to an instruction sent from the timing control unit whether the lateral line of the pixels in the rectangular area is an odd-numbered line or an even-numbered line, a sub-sampling circuit for performing the sub-sampling for the pieces of pixel data stored in the register in a quincunx method according to a judging result obtained in the odd-even judging circuit and the sample mode information stored in the group of transfer parameter registers to produce pieces of sampled pixel data and transforming the pieces of sampled pixel data into a piece of a combined pixel data corresponding to the lateral line according to an instruction sent from the timing control unit, and an output control circuit for outputting the combined pixel data of the lateral line transformed in the sub-sampling circuit according to an instruction sent from the timing control unit.
Accordingly, the sub-sampling for the pieces of pixel data can be performed according to the quincunx method by alternately selecting a group of pieces of pixel data corresponding to one odd-numbered lateral line and a group of pieces of pixel data corresponding to one even-numbered lateral line.
It is also preferred that the sub-sampling is performed by the data transforming unit according to a quincunx method to place pixels corresponding to the pieces of sub-sampled pixel data of one group of lateral lines at even-numbered positions on each lateral line and to place pixels corresponding to the pieces of sub-sampled pixel data of the other group of lateral lines at even-numbered positions on each lateral line.
Accordingly, the sub-sampling of pieces of pixel data of pixels placed at fixed longitudinal rows of the rectangular area can be prevented in the direct memory access transfer apparatus.